Project Overview
the goal of the project is to create a counter that counts from 0 to 80 and pauses the count at 80 until manually reset by a switch. The limitations are that the tens counter must be made from D flip flops and the ones counter from an msi chip.
Circuit
The difference between the design mode and pld mode is that design mode as all the parts as the part numbers and the pld mode has them by name. The pld mode is exportable to a pld device and the input and output connectors are pins on the device which then is able to be breadboarded.
Conclusions
the Small scale integration uses the flip flops individually while the msi is four flip flops prewired into one chip. The msi is limited to only counting from zero, and can not count higher than 15. The ripple effect is when the digital signal is delayed to the display causing glitches in the display. first I have a clock connected to a logic gate which is controlled by a switch which acts as a pause. from the switch it acts as a clock to the msi which counts from 0-9 once it reaches nine it activates a logic circuit which activates the clock on the ssi which acts as the tens counter, which counts fromm 0-8. once the count reaches 80 it activates another logic circuit which deactivates two transistors. these transistors pause the count and stop the tens counter from resetting. until the count is reset by a manual switch. The circuit pauses because the logic stops the clock when it detects 80 on the display. the 80 is detected by multiple and gates which detects an 8 on the tens counter and a 0 on the ones counter. I limited the count on the tens counter by detecting a nine and the ones counter detecting a 10. The other students did not use transistors as I did.